digitalverification.blogspot.com
Verification Blog: October 2008
http://digitalverification.blogspot.com/2008_10_01_archive.html
This blog is all about verification of Digital Designs. Wednesday, 15 October 2008. Verification Engineer required for Cadence Design Systems, Bangalore or Noida. 4 to 5 years. India, Bangalore or Noida. Responsibilities will include creating and customising design environments, design and verification methodologies. The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain. The candidate should possess the necessary engineering an...
digitalverification.blogspot.com
Verification Blog: December 2008
http://digitalverification.blogspot.com/2008_12_01_archive.html
This blog is all about verification of Digital Designs. Wednesday, 17 December 2008. Job openings at Cadence Design Systems, India (Bangalore and Noida). In this tough time, there are some openings at Cadence Design Systems for its India centers (Bangalore and Noida). Please have a look at the openings for more details here. Links to this post. Subscribe to: Posts (Atom). Job openings at Cadence Design Systems, India (Ban. Cadence Functional Verification Blog. Who is refering this blog?
digitalverification.blogspot.com
Verification Blog: May 2010
http://digitalverification.blogspot.com/2010_05_01_archive.html
This blog is all about verification of Digital Designs. Saturday, 8 May 2010. Generic/Parameter support in Mixed HDL Hierarchy Code Generator. I hope this small utility is helpful. I've thought one small enhancement to it. Now, you can select whether you need VHDL Generic or Verilog Parameterized examples code by selecting the checkbox. Please feel free to comment/enhancement. You can visit http:/ www.sandipgor.com/hdl gen.html. Links to this post. Subscribe to: Posts (Atom). Who is refering this blog?
tremaineconsultinggroup.com
Resources | Tremaine Consulting Group
http://tremaineconsultinggroup.com/resources
Resources (links to papers). Fuzzy Logic Motor Control. Improving PID motor control using Fuzzy logic as compared to ad-hoc non-linear control of boundary conditions. A method to determine the optimal move-time trajectory for an arbitrary dynamic system while meeting specified acoustic constraints. Thesis for Engineer Degree from Stanford University. Calculate the dynamic equations of a cantilevered MEMS device. Calculate the Au film thickness on a MEMS mirror to meet loss requirements.
poluekt.wordpress.com
poluekt — Konstantin Bragin
https://poluekt.wordpress.com/author/poluekt
Август 23, 2011. Xargs: многообразие вариантов использования habr.ru/p/248207/. How to Install Git 2.0.5 on CentOS/RHEL 7/6/5 and Fedora 22/21 tecadmin.net/install-git-2-. Блог на WordPress.com. Такие блоггеры, как:.
poluekt.wordpress.com
Recommend books — Konstantin Bragin
https://poluekt.wordpress.com/useful-things/recommended-books
Advanced Digital Design with Verilog HDL. The Verilog Hardware Description Language,. Donald E. Thomas, Philip R. Moorby. Verilog and SystemVerilog Gotchas. Stuart Sutherland, Don Mills. Practical Programming in Tcl and Tk. Brent B Weltch, Ken Jones, Jeffrey Hobbs. Writing Testbenches using SystemVerilog. Caner, Folk, Nguen. The C Programming Language. B Kernighan, D. Ritchi. Effective C : 55 Specific Ways to Improve Your Programs and Designs. Digital Design Principles and Practices. John F. Wakerly.
poluekt.wordpress.com
re — Konstantin Bragin
https://poluekt.wordpress.com/2011/08/23/re
Август 23, 2011. Добавить комментарий Отменить ответ. Заполните поля или щелкните по значку, чтобы оставить свой комментарий:. Адрес никогда не будет опубликован). Для комментария используется ваша учётная запись WordPress.com. ( Выход. Для комментария используется ваша учётная запись Twitter. ( Выход. Для комментария используется ваша учётная запись Facebook. ( Выход. Для комментария используется ваша учётная запись Google . ( Выход. Уведомлять меня о новых комментариях по почте.
poluekt.wordpress.com
CV — Konstantin Bragin
https://poluekt.wordpress.com/cv
Phone 7 (915) 220-30-25. Location: Russia, Moscow, Zelenograd. Date of birth: 09.10.1983. Since 02.2011 IDM-PLUS. ASIC Digital Design Engineer. Modelling of individual units. Logic sinthesis (with BSD/DFT). Control over functional verification. Cooperation with application engineers/test engineers/analog engineers/back-end command. 8212; development languages: Verilog/SystemVerilog. 8212; logic synthesis: Synopsys DC. 8212; formal verification: Synopsys Formality. 8212; version control systems: svn.