asics.chuckbenz.com

Chuck Benz's ASIC/FPGA pages

Chuck Benz ASIC and FPGA Design. I have been designing ASICs and FPGAs for over 20 years now, and want to share some of what I've learned, as well as some open source tools that are also the result of my experiences. I am sometimes available for part-time or full-time consulting in the Boston/Nashua area, short-term or long-term, for design or RTL code reviews, architecture discussions/reviews, design implementation, or formal verification. Chuck's generic SPI *****. Comments on Fifos, Ring Buffers.

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Chuck Benz's ASIC/FPGA pages | asics.chuckbenz.com Reviews

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Chuck Benz ASIC and FPGA Design. I have been designing ASICs and FPGAs for over 20 years now, and want to share some of what I've learned, as well as some open source tools that are also the result of my experiences. I am sometimes available for part-time or full-time consulting in the Boston/Nashua area, short-term or long-term, for design or RTL code reviews, architecture discussions/reviews, design implementation, or formal verification. Chuck's generic SPI *****. Comments on Fifos, Ring Buffers.

<META> KEYWORDS

1 hamming code

2 logic investigator

3 csrgen perl script

4 example csrs

5 updated aug '04

6 cbaf cgss v

7 and a testbed

8 encode v

9 decode v

10 validate 8b10b v

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hamming code,logic investigator,csrgen perl script,example csrs,updated aug '04,cbaf cgss v,and a testbed,encode v,decode v,validate 8b10b v,xcrraaaaaaaadddddddddddd,where,chuck benz

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Chuck Benz's ASIC/FPGA pages | asics.chuckbenz.com Reviews

https://asics.chuckbenz.com

Chuck Benz ASIC and FPGA Design. I have been designing ASICs and FPGAs for over 20 years now, and want to share some of what I've learned, as well as some open source tools that are also the result of my experiences. I am sometimes available for part-time or full-time consulting in the Boston/Nashua area, short-term or long-term, for design or RTL code reviews, architecture discussions/reviews, design implementation, or formal verification. Chuck's generic SPI *****. Comments on Fifos, Ring Buffers.

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asics.chuckbenz.com

1

Fifos and Ring Buffers

http://asics.chuckbenz.com/FifosRingBuffers.htm

Fifos and Ring Buffers. First draft, 9-December-2001, Chuck Benz, updated 15-jan-2002. The fifo is an often used logic/memory structure with broad utility. It is often used to pass wide data between asynchronous clock domains, and also as a storage element within a single clock domain. Usually there is empty and/or full indication that reflects the indexes indirectly. Verilog code of a typical fifo is shown below. This single clock design uses a memory that allows asynchronous reads any change on the...

2

Applying Hamming Code to blocks of data

http://asics.chuckbenz.com/HammingCode.html

Applying Hamming Code to blocks of data. August 21, 2001. Hamming code affords a straightforward way to protect a block of data against single bit errors. It allows any single bit error to be detected and corrected. This discussion will explain Hamming code basics and discuss modifications and applications. The intended audience is digital logic designers/engineers since the author is an engineer, mathematicians and computer scientists may cringe at some of the phrasing and terminology. Check[3] = 8 9 10...

3

Delay Commutators

http://asics.chuckbenz.com/delaycommutators.htm

How to Rotate Pipelined Data for FFTs. Often, data is present in a pipeline in a linear order, but a calculation is desired to operate on multiple indexes into the data with a "stride" or increment that needs to step across several pipeline stages. This is the case in a pipeline implementing FFT using radix2 or radix4 butterfly operations, or implementing other types of data transforms. If data in a pipeline is presented sequentially, 4 samples wide, it might look like so:. Let's look at how the data wou...

4

One-Hot Coding for State Machines in Verilog

http://asics.chuckbenz.com/OneHotCodingBestPractices.htm

Best Practices for One-Hot State Machine, coding in Verilog. There are 3 main points to making high speed state machines by one-hot encoding:. Use 'parallel case' and 'full case' directives on a 'case (1'b1)' statement. Style to represent the current state. Assign next state by:. Default assignment of 0 to state vector. Fully specify all conditions of next state assignments, including staying in current state. Also, these points are also recommended:. Use parameters to assign state encoding (or `define).

5

Sit-Link - virtual serial link

http://asics.chuckbenz.com/sitlink.html

A virtual serial link between logic simulations. Enabling simulations at different locations to be linked by PCI Express, SONET, Serial RapidIO, Ethernet, etc. Also, here is a marketing brief that I prepared. At present, sit-link consists of:. A linux application utilizing sockets that links over a network. A simulation model that collects serial data into batches that are sent as a network packet. The simulation model communicates with the linux application through "named pipes".

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Chuck Benz's ASIC/FPGA pages

Chuck Benz ASIC and FPGA Design. I have been designing ASICs and FPGAs for over 20 years now, and want to share some of what I've learned, as well as some open source tools that are also the result of my experiences. I am sometimes available for part-time or full-time consulting in the Boston/Nashua area, short-term or long-term, for design or RTL code reviews, architecture discussions/reviews, design implementation, or formal verification. Chuck's generic SPI Slave. Comments on Fifos, Ring Buffers.

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