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Digital Design & Dependability Research Group

Digital Design and Dependability Research Group. Reliability and diagnostics of electronic circuits, design of FPGA architectures with respect to self-diagnostics. Test generation and compression. Decomposition of combinational and sequential circuits with respect to their implementation. Synchronous and asynchronous logic synthesis. FPGA implementations of arithmetic units. Reconfigurable computing, FPGA-based accelerators. Acceleration of ECDSA-based cryptography algorithms. DDD research group poster 1.

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Digital Design and Dependability Research Group. Reliability and diagnostics of electronic circuits, design of FPGA architectures with respect to self-diagnostics. Test generation and compression. Decomposition of combinational and sequential circuits with respect to their implementation. Synchronous and asynchronous logic synthesis. FPGA implementations of arithmetic units. Reconfigurable computing, FPGA-based accelerators. Acceleration of ECDSA-based cryptography algorithms. DDD research group poster 1.

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Digital Design & Dependability Research Group | ddd.fit.cvut.cz Reviews

https://ddd.fit.cvut.cz

Digital Design and Dependability Research Group. Reliability and diagnostics of electronic circuits, design of FPGA architectures with respect to self-diagnostics. Test generation and compression. Decomposition of combinational and sequential circuits with respect to their implementation. Synchronous and asynchronous logic synthesis. FPGA implementations of arithmetic units. Reconfigurable computing, FPGA-based accelerators. Acceleration of ECDSA-based cryptography algorithms. DDD research group poster 1.

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Digital Design & Dependability Research Group

http://ddd.fit.cvut.cz/index.php?page=people

Digital Design and Dependability Research Group. Doc Ing. Hana Kubátová, CSc. CPU architecture, digital design. Ing Jaroslav Borecký, Ph.D. Self testing circuits based on FPGA. Borecjar@fit.cvut.cz. Prediction and analysis of mission critical systems dependability. Danhema1@fit.cvut.cz. Ing Radek Dobiáš, Ph.D. Fault-tolerant design in FPGA. Railway sefety devices with programable HW. Dobiasr@fit.cvut.cz. Doc Ing. Jiří Douša, CSc. Logic design, simulation. Dousa@fit.cvut.cz. Fiserp@fit.cvut.cz. Dynamic re...

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Digital Design & Dependability Research Group

http://ddd.fit.cvut.cz/index.php?page=main

Digital Design and Dependability Research Group. Reliability and diagnostics of electronic circuits, design of FPGA architectures with respect to self-diagnostics. Test generation and compression. Decomposition of combinational and sequential circuits with respect to their implementation. Synchronous and asynchronous logic synthesis. FPGA implementations of arithmetic units. Reconfigurable computing, FPGA-based accelerators. Acceleration of ECDSA-based cryptography algorithms. DDD research group poster 1.

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Εργαστήριο Σχεδίασης Ψηφιακών Ολοκληρωμένων Κυκλωμάτων και Συστημάτων. SKYTALE Group - CEID, University of Patras. Circuits and Systems Group, University of Thessaly. Digital Systems and Media Computing Laboratory, Hellenic Open University. VLSI Design lab, University of Patras. The Business and Technology Club. Digital Design and Dependability Research Group, Czech Technical University in Prague. DICES Lab @ 6ο Forum Ενέργειας. DICES Lab @ Forum Ανάπτυξης - Money Show 2016 Volume II.

fit.cvut.cz

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České vysoké učení technické v Praze. Raquo; 18103 Katedra číslicového návrhu. 18101 Katedra teoretické informatiky. 18102 Katedra softwarového inženýrství. 18103 Katedra číslicového návrhu. 18104 Katedra počítačových systémů. 18105 Katedra aplikované matematiky. 18103 Katedra číslicového návrhu. Vedoucí: doc. Ing. Hana Kubátová, CSc. kubatova[@]fit.cvut.cz tel: 2 2435 9840. Sekretariát: Ivana Holíková, Ivana.Holikova@fit.cvut.cz tel: 2 2435 9832. Výzkumné zaměření. Výzkumné skupiny. Ladislava.smitko...

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ddd.fit.cvut.cz

Digital Design & Dependability Research Group

Digital Design and Dependability Research Group. Reliability and diagnostics of electronic circuits, design of FPGA architectures with respect to self-diagnostics. Test generation and compression. Decomposition of combinational and sequential circuits with respect to their implementation. Synchronous and asynchronous logic synthesis. FPGA implementations of arithmetic units. Reconfigurable computing, FPGA-based accelerators. Acceleration of ECDSA-based cryptography algorithms. DDD research group poster 1.

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