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e-verificationBlog is designed to share/discuss topics on HVL verification using the concept of e-language
http://e-verification.blogspot.com/
Blog is designed to share/discuss topics on HVL verification using the concept of e-language
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e-verification | e-verification.blogspot.com Reviews
https://e-verification.blogspot.com
Blog is designed to share/discuss topics on HVL verification using the concept of e-language
e-verification.blogspot.com
e-verification: Importance Of Using Sampling Events in specman elite e-language
http://e-verification.blogspot.com/2009/04/importance-of-using-sampling-events-in.html
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Wednesday, April 15, 2009. Importance Of Using Sampling Events in specman elite e-language. In order to drive / sample signals correctly, there is a need to synchronize with the simulator. To achieve the above task there is a need to make use of the Specman elite Temporal Language Expression. The Temporal language of the e-language is the basis for capturing behavior over time for below purpose:. Specman elite p...
e-verification: Declaration of Specman e-language Basic Temporal Expressions
http://e-verification.blogspot.com/2009/04/declaration-of-specman-e-language-basic.html
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Wednesday, April 22, 2009. Declaration of Specman e-language Basic Temporal Expressions. Cadence Specman Elite e-language TE (Temporal Expression), is always associated with a sampling event indicating when the Temporal Expression needs to be evaluated by Specman elite e-language. The above expression indicates for every Sample-event that the Boolean Expression is true. 4) [Number] * TE. View my complete profile.
e-verification: March 2009
http://e-verification.blogspot.com/2009_03_01_archive.html
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Tuesday, March 31, 2009. Specman e-language supports constraint random generation. Specman e-language supports the concept of constrained random generation. Constraints are applied on struct members e.g Fields and methods. 183; Constraints are Boolean equations. 183; Constraints are declarative statements. Specman e-language categories the constrained mechansim as follows :. 3) Directed constrained Generation.
e-verification: Time Consuming Method (TCM) in specman e-language
http://e-verification.blogspot.com/2009/05/time-consuming-method-tcm-in-specman-e.html
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Thursday, May 7, 2009. Time Consuming Method (TCM) in specman e-language. Are defined as the methods that have the notion of time, as designated by their sampling event. 183; TCM's can be executed over several simulation cycles. Tcm name([arg: type,.]) [:return-type] @sampling-event is {. Required action parameters;. TCM’s are attached with sampling event. The sampling event fills two functions. Unit port u {.
e-verification: April 2009
http://e-verification.blogspot.com/2009_04_01_archive.html
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Wednesday, April 22, 2009. Declaration of Specman e-language Basic Temporal Expressions. Cadence Specman Elite e-language TE (Temporal Expression), is always associated with a sampling event indicating when the Temporal Expression needs to be evaluated by Specman elite e-language. The above expression indicates for every Sample-event that the Boolean Expression is true. 4) [Number] * TE. Wednesday, April 15, 2009.
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digitalverification.blogspot.com
Verification Blog: October 2008
http://digitalverification.blogspot.com/2008_10_01_archive.html
This blog is all about verification of Digital Designs. Wednesday, 15 October 2008. Verification Engineer required for Cadence Design Systems, Bangalore or Noida. 4 to 5 years. India, Bangalore or Noida. Responsibilities will include creating and customising design environments, design and verification methodologies. The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain. The candidate should possess the necessary engineering an...
digitalverification.blogspot.com
Verification Blog: December 2008
http://digitalverification.blogspot.com/2008_12_01_archive.html
This blog is all about verification of Digital Designs. Wednesday, 17 December 2008. Job openings at Cadence Design Systems, India (Bangalore and Noida). In this tough time, there are some openings at Cadence Design Systems for its India centers (Bangalore and Noida). Please have a look at the openings for more details here. Links to this post. Subscribe to: Posts (Atom). Job openings at Cadence Design Systems, India (Ban. Cadence Functional Verification Blog. Who is refering this blog?
digitalverification.blogspot.com
Verification Blog: May 2010
http://digitalverification.blogspot.com/2010_05_01_archive.html
This blog is all about verification of Digital Designs. Saturday, 8 May 2010. Generic/Parameter support in Mixed HDL Hierarchy Code Generator. I hope this small utility is helpful. I've thought one small enhancement to it. Now, you can select whether you need VHDL Generic or Verilog Parameterized examples code by selecting the checkbox. Please feel free to comment/enhancement. You can visit http:/ www.sandipgor.com/hdl gen.html. Links to this post. Subscribe to: Posts (Atom). Who is refering this blog?
digitalverification.blogspot.com
Verification Blog: September 2013
http://digitalverification.blogspot.com/2013_09_01_archive.html
This blog is all about verification of Digital Designs. Thursday, 26 September 2013. UVM-Multi Language solution from Cadence. 1) Connecting different components of different domains. 2) Transferring data/events from different domains. 3) Synchronizations of major phases. File : producer.sv. Uvm pkg: *;. Declare basic packet which will be passed to SC consumer. Declare SV producer which will communicate with SC consumer through out port. Declare out port. This port will be connected to SC consumer. Conne...
digitalverification.blogspot.com
Verification Blog: June 2009
http://digitalverification.blogspot.com/2009_06_01_archive.html
This blog is all about verification of Digital Designs. Thursday, 25 June 2009. IntelliGen is a new generation engine introduced in Specman 6.1 version onwards. It is a new generation engine which uses different generation algorithm from Specman's original generation engine PGen. Though PGen remains default generation engine, user can switch to IntelliGen by setting a configuration flag before loading any code. Specman config gen -default generator=IntelliGen. Based on addr hi lo. Define addr hi 0xFF;.
digitalverification.blogspot.com
Verification Blog: Cadence's Labs on Cloud
http://digitalverification.blogspot.com/2010/06/cadences-labs-on-cloud.html
This blog is all about verification of Digital Designs. Thursday, 24 June 2010. Cadence's Labs on Cloud. Have you ever wanted to try out any Cadence tools or VIPs evaluation without going through the process of getting evaluation licenses, software download and installation and all that logistic stuff? Now you can do all that without all that hassles. Cadence has tied with Xuropa for their cloud computing platform so that all you need is high speed broadband for any Cadence tools/VIPs evaluation.
digitalverification.blogspot.com
Verification Blog: Automatic Coverage Weight Calculator Utility
http://digitalverification.blogspot.com/2012/02/automatic-coverage-weight-calculator.html
This blog is all about verification of Digital Designs. Wednesday, 29 February 2012. Automatic Coverage Weight Calculator Utility. I hope people, who are looking such kind of solution will benefit from this post. Specman overall coverage grade is calculated in hierarchical manner by default. It means that coverage is calculated from leaf level to the top level in following manner. I've assumed that weight is not set manually and default weight value 1 is applied here. Config : config s;. C : bool;. Let's...
digitalverification.blogspot.com
Verification Blog: February 2012
http://digitalverification.blogspot.com/2012_02_01_archive.html
This blog is all about verification of Digital Designs. Wednesday, 29 February 2012. Automatic Coverage Weight Calculator Utility. I hope people, who are looking such kind of solution will benefit from this post. Specman overall coverage grade is calculated in hierarchical manner by default. It means that coverage is calculated from leaf level to the top level in following manner. I've assumed that weight is not set manually and default weight value 1 is applied here. Config : config s;. C : bool;. Let's...
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28/07/2011 at 3:38 AM. 15/08/2011 at 6:51 AM. Subscribe to my blog! Je m'apelle Chloé and j'ai 15 ans. Je suis B0NNE ;). Don't forget that insults, racism, etc. are forbidden by Skyrock's 'General Terms of Use' and that you can be identified by your IP address (66.160.134.62) if someone makes a complaint. Posted on Thursday, 28 July 2011 at 4:36 AM. Edited on Monday, 15 August 2011 at 6:52 AM. Je ne sais pas si tu te rends compte à quel point j'ai besoin de toi. Posted on Thursday, 28 July 2011 at 9:20 AM.
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e-verification
Blog is designed to share/discuss topics on HVL verification using the concept of e-language. Friday, August 5, 2011. Protocol Checkers for DUT state machine. In order to write a Protocol Checker for the DUT state machine we need to do the following. 1 Declare an enumerated type having the same propreties as of the DUT enumerated type. 2 Declare an e-port may be of simple port of inout type. 3 Declare an e-event for the corresponding DUT state machine value. Type state t : [ IDLE, SHIFT, SAMPLE];. On tra...
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