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Crosstalk | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/tag/crosstalk
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Posts Tagged ‘ Crosstalk. Are Guard Traces Worth It? Leave a comment ». Originally published in, The PCB Design Magazine. On the other side, merely separating the victim trace to at least three times the line width from the aggressor is good enough. The reasoning here is that crosstalk falls off rapidly with increased spacing anyways, and by adding a guard trace, you will already have at least three times the trace s...
appliedemtech.com
AET: Applied Electromagnetic Technology, LLC. - Application Notes & Papers
http://www.appliedemtech.com/bus_partners.html
ETS-Lindgren Universal Spherical Dipole Source (USDS) Product. Advanced Technology for Accurate Electromagnetic Measurements. Solomons, MD 20688.
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Backplane Architecture | Bert Simonovich's Design Notes
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Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Posts Tagged ‘ Backplane Architecture. Non-contact Interconnect: When Crosstalk Is Your Friend. Originally published in, The PCB Design Magazine. Nortel, a.k.a. Northern Telecom at the time, was looking to replace the computing module shelf of the DMS Supernode platform because it was projected to run out of steam a few years later. In order to address the issue, the system architects decided that a scala...No, something...
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Conductor loss | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/tag/conductor-loss
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Posts Tagged ‘ Conductor loss. Practical Conductor Roughness Modeling with Cannonballs. Leave a comment ». In the GB/s regime, accurate modeling of conductor losses is a precursor to successful high-speed serial link designs. Failure to model roughness effects can ruin you day. For example,. So what do cannon balls have to do with modeling copper roughness anyway? Figure 1 Comparisons of measured insertion loss of a 40 i...
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Via stubs | Bert Simonovich's Design Notes
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Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Posts Tagged ‘ Via stubs. PCB Vias Are Capacitive But Not Necessarily Capacitors. What do you mean by that? For this particular via geometry, the impedance is 33 Ohms and the excess via capacitance is 1.9pf. Even with a fast 50ps rise time at the source, by the time the signal reaches the via at the far end, the rise time will degrade due to dispersion caused by the lossy dielectric. In this example, after 23...If the to...
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Practical Conductor Roughness Modeling with Cannonballs | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/2015/04/25/practical-conductor-roughness-modeling-with-cannonballs
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Practical Conductor Roughness Modeling with Cannonballs. Leave a comment ». In the GB/s regime, accurate modeling of conductor losses is a precursor to successful high-speed serial link designs. Failure to model roughness effects can ruin you day. For example,. So what do cannon balls have to do with modeling copper roughness anyway? Figure 1 Comparisons of measured insertion loss of a 40 inch trace vs simulation. Ey...
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June | 2013 | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/2013/06
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Archive for June 2013. Dr Howard Johnson; a great teacher, mentor and friend. Leave a comment ». The other day, in my inbox, I received the link to the June 2013 electronic edition of EDN magazine. Dictionary.com defines a mentor as a wise and trusted counsellor or teacher. I was first introduced to his teachings by reading, High-speed Digital Design,. A handbook of black magic. When I look back now, I realized just how ...
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PCB via | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/tag/pcb-via
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Posts Tagged ‘ PCB via. PCB Vias Are Capacitive But Not Necessarily Capacitors. What do you mean by that? For this particular via geometry, the impedance is 33 Ohms and the excess via capacitance is 1.9pf. Even with a fast 50ps rise time at the source, by the time the signal reaches the via at the far end, the rise time will degrade due to dispersion caused by the lossy dielectric. In this example, after 23 i...If the to...
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To Know The Bit Error Rate Is To Know The Bit Error Ratio | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/2012/05/23/to-know-the-bit-error-rate-is-to-know-the-bit-error-ratio
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. To Know The Bit Error Rate Is To Know The Bit Error Ratio. Leave a comment ». Recently I came across a blog post titled, Can Oscilloscopes Really Calculate BERs. Written by Ransom Stephens. Before you discount this and say,. In mathematics, there can be only one answer. Stay with me here, and let me try to explain where I’m coming from. According to Merriam-Webster dictionary, the definition of ratio is,. Let’s Cal...
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Are Guard Traces Worth It? | Bert Simonovich's Design Notes
https://blog.lamsimenterprises.com/2013/04/12/are-guard-traces-worth-it
Bert Simonovich's Design Notes. Innovative Signal Integrity and Backplane Solutions. Are Guard Traces Worth It? Leave a comment ». Originally published in, The PCB Design Magazine. By definition, a guard trace is a trace routed coplanar between an aggressor line and a victim line. There has always been an argument on whether to use guard traces in high-speed digital and mixed signal applications to reduce the noise coupled from an aggressor transmission line to a victim transmission line. Software was us...
