mypotatochip.blogspot.com

mypotatochip

Thursday, March 17, 2011. Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results. Caused due to the glitches on power rails. Here image shows the key parasitic components associated with a p-well structure. How to avoid latch up? Introduction of gaurd rings. Increase in sub doping which inturn decreases value of Rs. Links to this post. Sunday, March 6, 2011. Links to this post. When Vin is hi...

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Thursday, March 17, 2011. Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results. Caused due to the glitches on power rails. Here image shows the key parasitic components associated with a p-well structure. How to avoid latch up? Introduction of gaurd rings. Increase in sub doping which inturn decreases value of Rs. Links to this post. Sunday, March 6, 2011. Links to this post. When Vin is hi...

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mypotatochip | mypotatochip.blogspot.com Reviews

https://mypotatochip.blogspot.com

Thursday, March 17, 2011. Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results. Caused due to the glitches on power rails. Here image shows the key parasitic components associated with a p-well structure. How to avoid latch up? Introduction of gaurd rings. Increase in sub doping which inturn decreases value of Rs. Links to this post. Sunday, March 6, 2011. Links to this post. When Vin is hi...

INTERNAL PAGES

mypotatochip.blogspot.com

1

mypotatochip: Apr 8, 2010

http://mypotatochip.blogspot.com/2010_04_08_archive.html

Thursday, April 8, 2010. 1Floor plan should be started with I/Os at the periphery (depending on package design). 2The blocks in the chip which require special design needs should be accommodated. For ex -PLL,analog block,blocks that require different voltage , block that work with double speed clock.Suppose a flash memory has high programming voltage input then it should be placed closer to the i/o pins. 5It is easy to floor plan the same size blocks so small blocks should be grouped together. 1Major des...

2

mypotatochip: Apr 20, 2010

http://mypotatochip.blogspot.com/2010_04_20_archive.html

Goal and objectives of the Floor plan and its Eval. Tuesday, April 20, 2010. Goal and objectives of the Floor plan and its Evaluation. The goals of floor planning are to:. Defining the core area, aspect ratio . Arrange the blocks on a chip. Decide the location of the I/O pads. Decide the location and number of the power pads. Decide the type of power distribution. Floor planning control parameters like aspect ratio, core utilization are defined as follows:. Core limited :Core logic determines the die size.

3

mypotatochip: Apr 5, 2010

http://mypotatochip.blogspot.com/2010_04_05_archive.html

Why i would like to become a physical design engin. What is physical design? What do you require for doing physical design? Monday, April 5, 2010. Why i would like to become a physical design engineer? So that i would get a chance to visit fab once in my lifetime,hoping for the best. Links to this post. What is physical design? The process of converting the design of a system into layout ,which can then be fabricated is known as physical design. Links to this post. 5Synopsys design constraints (SDC).

4

mypotatochip: Mar 6, 2011

http://mypotatochip.blogspot.com/2011_03_06_archive.html

Sunday, March 6, 2011. Links to this post. Subscribe to: Posts (Atom).

5

mypotatochip: Latch Up

http://mypotatochip.blogspot.com/2011/03/latch-up.html

Thursday, March 17, 2011. Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results. Caused due to the glitches on power rails. Here image shows the key parasitic components associated with a p-well structure. How to avoid latch up? Introduction of gaurd rings. Increase in sub doping which inturn decreases value of Rs. Subscribe to: Post Comments (Atom).

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Thursday, March 17, 2011. Latch-up is a condition in which parasitic components give rise to the low-resistance conducting path between the power rails i.e. vdd to Vss causing disastrous results. Caused due to the glitches on power rails. Here image shows the key parasitic components associated with a p-well structure. How to avoid latch up? Introduction of gaurd rings. Increase in sub doping which inturn decreases value of Rs. Links to this post. Sunday, March 6, 2011. Links to this post. When Vin is hi...

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