vlsiarch.ecen.okstate.edu vlsiarch.ecen.okstate.edu

vlsiarch.ecen.okstate.edu

OKLAHOMA STATE UNIVERSITY

VLSI Computer Architecture Research Group. Welcome to our research group! Note: All opinions, findings, conclusions, and recommendations expressed throughout this website are those of the VLSI Computer Architecture Research Group and do not necessarily reflect the views of any of our supporters. Professor James E. Stine, Jr., Director. VLSI Computer Architecture Research Group. Electrical and Computer Engineering Department. Stillwater, OK 74078. Jamesstine AT okstate.edu. Latest News and Events.

http://vlsiarch.ecen.okstate.edu/

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OKLAHOMA STATE UNIVERSITY | vlsiarch.ecen.okstate.edu Reviews
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VLSI Computer Architecture Research Group. Welcome to our research group! Note: All opinions, findings, conclusions, and recommendations expressed throughout this website are those of the VLSI Computer Architecture Research Group and do not necessarily reflect the views of any of our supporters. Professor James E. Stine, Jr., Director. VLSI Computer Architecture Research Group. Electrical and Computer Engineering Department. Stillwater, OK 74078. Jamesstine AT okstate.edu. Latest News and Events.
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5 publications
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OKLAHOMA STATE UNIVERSITY | vlsiarch.ecen.okstate.edu Reviews

https://vlsiarch.ecen.okstate.edu

VLSI Computer Architecture Research Group. Welcome to our research group! Note: All opinions, findings, conclusions, and recommendations expressed throughout this website are those of the VLSI Computer Architecture Research Group and do not necessarily reflect the views of any of our supporters. Professor James E. Stine, Jr., Director. VLSI Computer Architecture Research Group. Electrical and Computer Engineering Department. Stillwater, OK 74078. Jamesstine AT okstate.edu. Latest News and Events.

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vlsiarch.ecen.okstate.edu vlsiarch.ecen.okstate.edu
1

OKLAHOMA STATE UNIVERSITY

http://vlsiarch.ecen.okstate.edu/team

James E. Stine, Jr., Director. Post Doctorate and Visiting Scholars. Robert Elliott, M.S., December 2014. Mehedi Sarwar, Ph.D., May 2014, First Job: Intel. Masoud Sadeghian, Ph.D., May 2014, First Job: Abreezio. Son Bui, Ph.D. Harsha Choday, M.S., May 2009. Jonathan Holden, M.S., May 2009. Eric Schubert, M.S., May 2012. Manju Subbarayappa, M.S., May 2013. Jun Chen, Ph.D., December 2008, First Job: Avalink. Ivan Castellanos, Ph.D., May 2008, First Job: Intel. 8211; Professor James E. Stine, Jr.

2

OKLAHOMA STATE UNIVERSITY

http://vlsiarch.ecen.okstate.edu/publications

J Chen and J. E. Stine, “Extensions of Parallel Prefix Structures for Module $2 n-1$ Adders” in International Conference on Application-Specific Systems, Architectures, and Processors, Boston, Massachusetts, 2009 (in press). I Castellanos, J. Stine, Experiments for Decimal Floating-Point Division by Recurrence. Proceedings of the IEEE Conference on Signals, Systems and Computers, Asilomar, 2006. J Stine and M. J. Schulte, A combined two’s complement and IEEE-compliant floating-point comparator, P...J Gra...

3

OKLAHOMA STATE UNIVERSITY

http://vlsiarch.ecen.okstate.edu/flow

System on Chip (SoC) Design Flows. MOSIS SCMOS Cell Documentation. Design Flow and Library Integration. SoCks and VHDL Flow/Tutorial. SCMOS AND SRC Download. FreePDK: Unleashing VLSI to the Masses. Oklahoma State University System on Chip (SoC). Design Flows for use with Magic, Cadence, Synopsys, and MOSIS. The following pages give information regarding design flows for System on Chip designs that were developed for use at Oklahoma State University for use with MOSIS SCMOS SUBM process. Cadence is a trad...

4

OKLAHOMA STATE UNIVERSITY

http://vlsiarch.ecen.okstate.edu/dividesqrt

This site discusses some of the tools related to our research group. High Radix Divide/Multiply Architectures using Scaling. These designs discuss the implementations within the architecture for our radix 512 divide and. Combined divide and multiply that was discussed during 2010 Asilomar Conference on Signals, Systems, and Computers. PowerPoint Slides (pptx) (pdf). 32-bit Plain Verilog files with SBTM (zip). 32-bit Modified Verilog files with no CPA and SBTM (zip). PowerPoint Slides (pptx) (pdf).

5

OKLAHOMA STATE UNIVERSITY

http://vlsiarch.ecen.okstate.edu/chips

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VLSI Computer Architecture Research Group. Welcome to our research group! Note: All opinions, findings, conclusions, and recommendations expressed throughout this website are those of the VLSI Computer Architecture Research Group and do not necessarily reflect the views of any of our supporters. Professor James E. Stine, Jr., Director. VLSI Computer Architecture Research Group. Electrical and Computer Engineering Department. Stillwater, OK 74078. Jamesstine AT okstate.edu. Latest News and Events.

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